- The number of chip ID bits remains at three, allowing up to eight stacked chips.
- A third bank group bit (BG2) was added, allowing up to eight bank groups.
- The maximum number of banks per bank group remains at four.
- The number of row address bits remains at 17, for a maximum of 128K rows.
- One more column address bit (C10) is added, allowing up to 8192 columns (1 KB pages) in ×4 chips.
- The least-significant three column address bits (C0, C1, C2) are removed; all reads and writes must begin at a column address which is a multiple of eight.
- One bit is reserved for addressing expansion as either a fourth chip ID bit (CID3) or an additional row address bit (R17).
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